The present application relates to semiconductor technology, and more particularly to a semiconductor structure including a fin stack structure of, from bottom to top, a first semiconductor material fin portion, an insulator fin portion and a second semiconductor material fin portion. The present application also relates to a method of forming such a semiconductor structure.
The continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. The use of non-planar semiconductor devices such as, for example, Fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. FinFETs can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
In such non-planar semiconductor devices, a first set of semiconductor fins is formed within a first device region in which a first conductivity type device (i.e., n-FET or p-FET) can be subsequently formed, and a second set of semiconductor fins, which lie laterally adjacent to the first set of semiconductor fins, is formed in a second device region in which a second conductivity type device, that is opposite to the first conductivity type device, can be subsequently formed. A trench isolation structure is typically formed between the first and second device regions.
Stacked semiconductor fins in which the semiconductor fins are formed one atop another afford higher density than their non-stacked semiconductor fin counterparts. In devices containing stacked semiconductor fins, tensily strained semiconductor fins for providing n-FET devices are formed in one area of the substrate, while compressively strained semiconductor fins for p-FET devices are formed in another area that is laterally adjacent to the area including the n-FET devices.